The present invention relates to the field of dynamic random access memory (DRAM); more specifically, it relates to a compilable DRAM and a method for designing the compilable DRAM.
A compilable DRAM is a DRAM generated by a DRAM compiler. A DRAM compiler is a computer program containing algorithms based on a methodology that can synthesize different memory configurations to satisfy a customer""s needs for an embedded DRAM in their circuit design. Generally, these are custom designs for application specific integrated circuits (ASICs). The specific DRAM configuration is determined by the customers specification as to memory size, word width, number of words, and number of memory arrays. Compilable DRAMs are desirable because they are denser than SRAMs (static random access memory) and take up less space. In some cases, the technology (ground rules, materials, processes and performance specifications) of DRAMs may match the technology of other macros in the ASIC more closely than the technology of a SRAM.
FIG. 1 is a diagram of a portion of a DRAM device. In FIG. 1, DRAM device 100 is comprised of sets of memory units 105, each memory unit containing multiple DRAM arrays 110. DRAM arrays 110 are comprised of arrays of individual DRAM cells. The number of DRAM cells in each DRAM array 100 can range from just a few to many millions depending upon the specific application the DRAM device is designed for. DRAM devices 100 also include sets of wordline drivers 115. Each wordline driver 115 drives wordline signals onto wordlines 120. In general, each wordline 120 is comprised of a set of local wordlines connected to groups of DRAM cells within DRAM blocks 110. Local wordlines are strapped together in series to form global wordlines that run the length of memory units 105. There is one wordline driver for each DRAM unit 105. All wordlines 120 in a given memory unit 105, run through, and are coupled to memory cells in each DRAM array 110 of the memory unit. DRAM device 100 further includes sets of bitline drivers 125. Each bitline driver drives data signals to bitline pairs 130. Bitline pairs 130 run orthogonal to wordlines 120. Bitline pairs 130 are coupled to memory cells in one DRAM array 110 of each memory unit 105.
Because of the length of memory units 105 and the fact that wordlines 120 have a finite resistance, a signal impressed on any wordline of any wordline pair will arrive at the DRAM array 110 closest to wordline driver 115 before the signal arrives at the DRAM array farthest from the wordline driver. In advanced DRAM technology, the local wordline are usually formed polysilicon and the straps of metal. Since the metal straps have a sheet resistance of 0.12 ohms/sq. and polysilicon has a sheet resistance of about 300 to 400 ohms/sq. the wordline delay is mainly a function of the resistance/capacitance of the local wordlines for short memory units 105. For longer memory units 105, the delay becomes a complex function of metal and polysilicon delays.
FIG. 2 is a timing diagram for the DRAM device of FIG. 1. In FIG. 2, a wordline signal 150A is the signal reaching the closest DRAM array 110 and a wordline signal 150B is the signal reaching the farthest DRAM array 110. The difference in time between arrivals of the signal is wordline delay xe2x80x9cD.xe2x80x9d After a bitline charge delay xe2x80x9cd1,xe2x80x9d from wordline signal 150A, during which a bitline 155A signal and a bitline-not signal 165A build charge, bitline/bitline-not amplifiers of the closest DRAM array 110, turn on (set) to boost the signal voltage of the bitline and bitline-not signals. Similarly, after a bitline charge delay xe2x80x9cd2,xe2x80x9d from wordline signal 150B, during which a bitline 155B signal and a bitline-not signal 165B build charge, bitline/bitline-not amplifiers of the farthest DRAM array 110 turn on (set) to boost the signal voltage of the bitline and bitline-not signals. Because of wordline delay xe2x80x9cD,xe2x80x9d the set times of the bitline/bitline amplifiers of the closest DRAM array 110 and the bitline/bitline-not amplifiers of the farthest DRAM array 110 must be delayed by the wordline delay xe2x80x9cD.xe2x80x9d In a fixed size DRAM this is not a significant problem as the length of wordlines pairs 120 are fixed and known so a delay device circuit can be designed to simulate the wordline delay xe2x80x9cDxe2x80x9d and then incorporated into the circuit design to delay turn on (set) of the bitline/bitline-not amplifiers of farthest DRAM array 110, as well as all the intervening DRAM arrays, until the appropriate time. However, in a compilable DRAM, the length is not fixed or known ahead of time, so this approach is not very effective.
FIG. 3 is a schematic diagram of a method of setting timing in a static random access memory (SRAM) device. In FIG. 3, SRAM device 165 includes a closest SRAM array 170A, a farthest SRAM array 170B and a wordline driver 175. Wordline driver 175 drives wordline signals onto a multiplicity of wordlines 180 running from closest SRAM array 170A to farthest SRAM array 170B. Wordlines 180 are coupled to memory cells in each SRAM array of SRAM device 165. A multiplicity of closest bitlines 185A run through closest SRAM array 170A, orthogonal to wordlines 180, and are coupled to cells in the closest SRAM array. A multiplicity of farthest bitlines 185B run through closest SRAM array 170B, orthogonal to wordlines 180, and are coupled to cells in the farthest SRAM array. SRAM device 165 also includes a reference SRAM array 190 and a reference wordline driver 195. Reference wordline driver 195 drives dummy wordline signals onto a reference wordline 200. Reference wordline 200 has the same length and is otherwise a physical replica of wordlines 180. The purpose of reference wordline 200 is to as act a resistive delay model of wordlines 180. Coupled to reference wordline 200, at the end opposite from reference wordline driver 195, is sense device 205. In this example, sense device 205 is a simple inverter. Sense device 205 is used to turn on (set) bitline amplifiers for farthest bitlines 185B. If there are intervening SRAM arrays between closest SRAM array 170A and farthest SRAM array 170B, additional reference wordlines of appropriate length may be placed in reference SRAM array, with additional sense devices for setting bitlines in intervening SRAM arrays, attached thereto.
This approach does not work for an advanced technology compilable DRAM for two reasons. First, is the problem of the composition of wordlines. SRAM wordlines are comprised of master wordlines and local wordlines, each having drivers. In an SRAM, both master and local wordlines are metal and the delay is a straightforward low value metal RC delay (a metal wordline has a sheet resistance of about 0.12 ohms/sq.). As previously discussed, in a DRAM, the wordline is a metal/polysilicon combination with metal straps stitching together polysilicon local wordlines. Second, ground rules for wordlines in SRAM cells are generally larger than the ground rules for wordlines in a DRAM. This forces the use of dummy local wordlines to be placed outside the array of active memory cells for the photolithographic reasons described above. This problem is illustrated in FIG. 4 and described next.
FIG. 4 is an illustration of printed wordlines for an advanced DRAM device. Illustrated in FIG. 4, is an active local wordline set 210 is comprised of an outer active local wordline 215 and inner active local wordlines 220. Also illustrated in FIG. 4, is a dummy local wordline set 225. Dummy local wordline set 225 comprises an inner dummy local wordline 230, a middle dummy local wordline 235 and an outer dummy local wordline 240. Inner dummy local wordline 230 is most adjacent to outer active local wordline 215. One purpose of dummy local wordline set is to mitigate proximity effects on wordlines in active local wordline set 210. All of active local wordlines are shown as printing as designed. Inner dummy local wordline 230 is shown printing somewhat distorted, middle dummy local wordline 235 is shown printing greatly distorted and outer dummy local wordline 240 is only partially printed and is not continuous. If dummy local wordline set 225 were not present, then active local wordlines 215 and 220 would have printed with the distortions illustrated for the dummy local wordlines. Clearly, the inner and middle dummy local wordlines 230 and 235 are not physical replicas of any active local wordline in active local wordline set 210. Inner and middle dummy local wordlines 230 and 235 have different widths therefore different resistances and hence different delays, than any of the wordlines in active local wordline set 210 and would be useless as reference wordlines as illustrated in FIG. 3 and described above.
A first aspect of the present invention is a semiconductor memory comprising: a memory cell adapted to store a bit; a wordline and a bitline coupled to the memory cell; a primary sense amplifier coupled to the bitline to receive a signal representing the stored bit when the wordline is active; a wordline driver coupled to activate the wordline; and a primary delay device adapted to produce a first delay selected from a range of selectable delays, the primary delay device adapted to compensate for signal propagation delay along the wordline.
A second aspect of the present invention is a semiconductor memory, comprising: a memory cell adapted to store a bit; a wordline and a local bitline coupled to the memory cell; a primary sense amplifier coupled to the local bitline pair to receive a signal representing the stored bit when the wordline is active, the primary sense amplifier coupled to a global bitline pair; a secondary sense amplifier coupled between the global bitline pair and a data driver; a wordline driver coupled to activate the wordline; a primary delay device having a selectable delay, coupled between a wordline driver replica and the primary sense amplifier, the primary delay device producing a first delay signal to time the primary sense amplifier; and a secondary delay device having a selectable delay, coupled between the primary delay device and the secondary sense amplifier to receive the first delay signal, the secondary delay device producing a second delay signal to time the secondary sense amplifier.
A third aspect of the present invention is a method of compensating for propagation delays in a memory device, comprising: providing a memory cell adapted to store a bit; coupling a wordline and a local bitline to the memory cell, coupling a primary sense amplifier between the local bitline and a global bitline, the primary sense amplifier to receiving a signal representing the stored bit when the wordline is active; coupling a secondary sense amplifier between the global bitline and a data driver; coupling a wordline driver to activate the wordline; coupling a primary delay device having a selectable delay between a wordline driver replica and the primary sense amplifier, the primary delay device producing a first delay signal to time the primary sense amplifier; and coupling a secondary delay device having a selectable delay between the primary delay device and the secondary sense amplifier to receive the first delay signal, the secondary delay device producing a second delay signal to time the secondary sense amplifier.
A fourth aspect of the present invention is a computer-readable storage medium encoding a method of designing a semiconductor memory of the type in which a bit stored in a memory cell is transferred to a bitline of a bitline pair coupled to a primary sense amplifier, the primary sense amplifier coupled to a secondary sense amplifier, the secondary sense amplifier coupled to a data driver through a global data line, the bit further being accessed by activating a wordline, the method comprising: calculating a worst case wordline signal delay based upon the number of bitline pairs coupled to a wordline in the memory; and inserting a primary delay device into the memory to time the primary sense amplifiers based upon the calculated worst case wordline signal delay.